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pipeline burst cache Last modified: Friday, May 25, 2001
A type of memory cache built into many modern DRAM controller and chipset designs. Pipeline burst caches use two techniques - a burst mode that pre-fetches memory contents before they are requested, and pipelining so that one memory value can be accessed in the cache at the same time that another memory value is accessed in DRAM. The purpose of pipeline burst caches is to minimize wait states so that memory can be accessed as fast a possible by the microprocessor. The term is often abbreviated as PBC.
Cache Transfer Technologies and Timing Describes the factors that directly influence the performance of the level 2 cache, including cache bursting and pipeline burst cache. Also included is information on system timing and a comparison of transfer technology. This page is from "The PC Guide".	Related Categories Caches Related Terms BEDO DRAM burst mode cache DRAM pipelining SDRAM wait state pipeline burst cache Products : Compare Prices & Save on Motherboards at DealTime! Search by brand or type to find the best price across 100s of stores! Top Store Offers: eBay  99.00Dell.Resell the place for the best deals!! You are buying a Brand New DELL DIMENSION 2400 MOTHERBOARD F5949 Microprocessor type Intel® Pentium® 4 or... Compare all matches: 1 Store Offers